CMOS比较器

High speed comparator design used was taken from [6] and adapted to meet the required speed and accuracy. Figure 2.7 shows the final design schematics of the clocked voltage comparator used. The design consists of pre-amplification stage followed by a decision making stage. The output is latched during the Latch. After the comparison is made a digital level outputs are produced. M0 and M1 transistors sense the change at the input and accordingly activate M8, M11 and M9, M10 current mirror pairs. Depending on the difference in the input signals, one of the transistor pairs will be turned on and other will be turned off. These transistors are part of the pre-amplification stage. Depending on the decision of the pre-amplification stage, M4 and M5 transistor configuration of the decision making stage will accordingly turn on/off to determine comparator’s digital output. M7, M19 and M6, M20 are inverter pairs which will buffer the output and restore the full logic levels. NMOS transistor of the inverter pairs (M7 and M6) are sized to be larger than the PMOS transistors because it took longer for the digital output to settle to level low than high. To avoid this problem NMOS transistors were increased to gain on speed. Also, this particular design has pre-charged output that will erase memory from the previous comparison. Whenever comparator is not active the output is pulled high. This allows PMOS transistors M19 and M20 to be minimum sized because if the comparator’s decision is logic high the output has already been pre-charged. Transistors M12, M13 and M14 pre-charge the output to logic high during the comparator’s off time. M16 and M17 transistors function is to turn the decision making stage off during comparator’s off time. For example: During Latch, if Vin+ of the comparator input is higher than Vin- than M8,M11 pair will turn on and M9, M10 pair will turn off. This will turn M4 and M7 on and M5 and M6 off. M6 being off will active M20 and the output will be a logic high, which it should when Vin+ is greater than Vin-.

Current comparator design can have a signal and its compliment as outputs. Comparator implemented does not supply as an output a compliment of the signal. Instead the compliment signal is obtained through the inversion of the comparator output. Inverter is part of the sub-DAC block. This was done to avoid any indecisive comparator outputs. Four inverters whose sizes showed to be crucial in determining the speed of the converter were M10 and M11 of the pre-amplification stage and M4 and M5 the decision making stage. These inverters were optimized to meet the speed and accuracy needed. Simulation results for the voltage comparator are discussed later on.